1 ps8317a 03/22/01 pin configuration block diagram description the pi6c185-00 is a high-speed low-noise 1-7 non-inverting buffer designed for sdram clock buffer applications. this buffer is intended to be used with the pi6c10x clock genera- tor for intel architecture-based mobile systems. at power up all sdram output are enabled and active. the i 2 c serial control may be used to individually activate/deactivate any of the 7 output drivers. note: purchase of i 2 c components from pericom conveys a license to use them in an i 2 c system as defined by philips. sdram6 sdram2 sdram1 sdram0 buf_in sdata sclock sdram3 i 2 c i/o product features high-speed, low-noise non-inverting 1-7 buffer switching speed up to 140 mhz (pi6c185-00a)* supports up to three mobile sdram dimms low skew (<250ps) between any two output clocks i 2 c serial configuration interface multiple v dd , v ss pins for noise reduction 3.3v power supply voltage 20-pin tssop (l) and qsop (q) packages 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 precision 1-7 clock buffer pi6c185-00 1 2 3 v ss 4 buf_in 5 sdram1 6 sdram2 7 v ss 8 v dd 9 sdata 10 v dd sdram5 v ss sdram4 sdram3 v ss v ss 20 sclk 19 18 17 16 15 14 13 12 11 v dd sdram0 v dd v dd sdram6 20-pin l, q * maximum operating frequencies: pi6c185-00 = 125 mhz; pi6c185-00a = 140 mhz.
pi6c185-00 precision 1-7 clock buffer 2 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pin description pi6c185-00 i 2 c address assignment pi6c185 serial configuration map byte0: sdram active/inactive register (1 = enable, 0 = disable) note: inactive means outputs are held low and are disabled from switching 6 a5 a4 a3 a2 a1 a0 aw / r 11010 0 1 0 t i b# n i pn o i t p i r c s e d 7 t i b5 1) e v i t c a n i / e v i t c a ( 4 m a r d s 6 t i b4 1) e v i t c a n i / e v i t c a ( 3 m a r d s 5 t i b- ) 0 o t e z i l a i t i n i ( c n 4 t i b7 ) e v i t c a n i / e v i t c a ( 2 m a r d s 3 t i b- ) 0 o t e z i l a i t i n i ( c n 2 t i b- ) 0 o t e z i l a i t i n i ( c n 1 t i b3 ) e v i t c a n i / e v i t c a ( 1 m a r d s 0 t i b2 ) e v i t c a n i / e v i t c a ( 0 m a r d s byte1: sdram active/inactive register (1 = enable, 0 = disable) t i b# n i pn o i t p i r c s e d 7 t i b- ) 0 o t e z i l a i t i n i ( c n 6 t i b- ) 0 o t e z i l a i t i n i ( c n 5 t i b- ) 0 o t e z i l a i t i n i ( c n 4 t i b- ) 0 o t e z i l a i t i n i ( c n 3 t i b- ) 0 o t e z i l a i t i n i ( c n 2 t i b- ) 0 o t e z i l a i t i n i ( c n 1 t i b9 1) e v i t c a n i / e v i t c a ( 6 m a r d s 0 t i b8 1) e v i t c a n i / e v i t c a ( 5 m a r d s n i pl a n g i se p y t. y t qn o i t p i r c s e d 9 1 , 8 1 , 5 1 , 4 1 , 7 , 3 , 2] 6 . 0 [ m a r d si7 s t u p t u o k c o l c d e r e f f u b 5n i _ f u bi1 t u p n i r e f f u b k c o l c 0 1a t a d so / i1 i r o f a t a d l a i r e s 2 . p u - l l u p l a n r e t n i , e c a f r e t n i c 1 1k l c si1 i r o f k c o l c l a i r e s 2 p u - l l u p l a n r e t n i , e c a f r e t n i c 0 2 , 6 1 , 9 , 6 , 1v d d r e w o p5 y l p p u s r e w o p v 3 . 3 7 1 , 3 1 , 2 1 , 8 , 4v s s d n u o r g5d n u o r g
pi6c185-00 precision 1-7 clock buffer 3 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2-wire i 2 c control the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c185-00 is a slave receiver device. it can not be read back. sub addressing is not supported. to change one of the control bytes, all preceding bytes must be sent. every bite put on the sdata line must be 8-bits long (msb first), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclk is low. exceptions: a high to low transition on sdata while sclk is high indicates a ?start? condition. a low to high transition on sdata while sclk is high is a ?stop? condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low = write to addressed device). if the device?s own address is detected, pi6c185-00 generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. following acknowledgement of the address byte (0d2h), two more bytes must be sent: 1. ?command code? byte, and 2. ?byte count? byte. although the data bits on these two bytes are ?don?t care,? they must be sent and acknowledged. storage temperature ......................................... ?65c to +150c ambient temperature with power applied ........... ?0c to +70c 3.3v supply voltage to ground potential ............. ?0.5v to +4.6v dc input voltage .................................................. ?0.5v to +4.6v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. supply current (v dd = +3.465v, c load = max.) l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. p y t. x a ms t i n u i d d t n e r r u c y l p p u sz h m 0 = n i _ f u b3 a m i d d t n e r r u c y l p p u sz h m 6 6 . 6 6 = n i _ f u b5 8 i d d t n e r r u c y l p p u sz h m 0 . 0 0 1 = n i _ f u b0 3 1 i d d t n e r r u c y l p p u sz h m 3 . 3 3 1 = n i _ f u b0 2 2 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.)
pi6c185-00 precision 1-7 clock buffer 4 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 sdram clock buffer operating specification ac timing dc operating specifications (v dd = +3.3v 5%, t a = 0c - 70c) l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. x a ms t i n u e g a t l o v t u p n i v h i e g a t l o v h g i h t u p n iv d d 0 . 2v d d 3 . 0 + v v l i e g a t l o v w o l t u p n iv s s 3 . 0 -8 . 0 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < d d 5 -5 +a m v d d % 5 v 3 . 3 = ] 9 - 0 [ v h o e g a t l o v h g i h t u p t u oi h o a m 1 ? =4 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 =4 . 0 c t u o e c n a t i c a p a c n i p t u p t u o 6 f p c n i e c n a t i c a p a c n i p t u p n i 5 l n i p e c n a t c u d n i n i p 7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c l o b m y sr e t e m a r a ps n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 2 =4 5 ? a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 3 1 . 3 =6 4 - i n i m l o t n e r r u c n w o d - l l u pv t u o v 0 . 1 =4 5 i x a m l o t n e r r u c n w o d - l l u pv t u o v 4 . 0 =3 5 t h r m a r d sy l n o m a r d s e t a r e g d e e s i r t u p t u ov 4 . 2 - v 4 0 @ % 5 v 3 . 35 . 14 s n / v t h t m a r d sy l n o m a r d s e t a r e g d e l l a f t u p t u ov 4 . 0 - v 4 . 2 @ % 5 v 3 . 35 . 14 l o b m y sr e t e m a r a p z h m 6 6z h m 0 0 1z h m 3 . 3 3 1 s t i n u . n i m. x a m. n i m. x a m. n i m. x a m t p k d s d o i r e p k l c m a r d s0 . 5 15 . 5 10 . 0 15 . 0 15 . 70 . 8 s n t h k d s e m i t h g i h k l c m a r d s6 . 53 . 32 . 2 t l k d s e m i t w o l k l c m a r d s3 . 51 . 30 . 2 t e s i r d s e m i t e s i r k l c m a r d s5 . 10 . 45 . 10 . 44 . 10 . 4 s n / v t l l a f d s e m i t l l a f k l c m a r d s5 . 10 . 45 . 10 . 44 . 10 . 4 t h l p y a l e d p o r p h l r e f f u b m a r d s0 . 10 . 50 . 10 . 50 . 10 . 5 s n t l h p y a l e d p o r p l h r e f f u b m a r d s0 . 10 . 50 . 10 . 50 . 10 . 5 t l z p t , h z p y a l e d e l b a n e r e f f u b m a r d s0 . 10 . 80 . 10 . 80 . 10 . 8 t z l p t , z h p y a l e d e l b a s i d r e f f u b m a r d s0 . 10 . 80 . 10 . 80 . 10 . 8 e l c y c y t u dv 5 . 1 t a d e r u s a e m5 45 55 45 55 45 4% t w k s d s w e k s t u p t u o o t t u p t u o m a r d s0 5 20 5 20 5 2s p
pi6c185-00 precision 1-7 clock buffer 5 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1.5v 1.5v t phl t plh 1.5v 1.5v input waveform output waveform output buffer test point 2.4 1.5 0.4 tsdkh tsdkp 3.3v clocking interface (ttl) tsdkl t sdfall t sdrise test load figure 1. clock waveforms notes: 1. maximum rise/fall times are guaranteed at maximum specified load. 2. minimum rise/fall times are guaranteed at minimum specified load. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 w resistor in parallel. minimum and maximum expected capacitive loads design guidelines to reduce emi 1. place series r s resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10pf. r s series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of ?vias? of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. k c o l cd a o l . n i md a o l . x a ms t i n us e t o n m a r d s0 20 3f p m m i d m a r d s n o i t a c i f i c e p s
pi6c185-00 precision 1-7 clock buffer 6 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pcb layout suggestion note: this is only a suggested layout. there may be alternate solutions depending on actual pcb design and layout. as a general rule, c1-c5 should be placed as close as possible to their respective v dd . recommended capacitor values: c1-c5 .............. 0.1 m f, ceramic c6 .................. 22 m f figure 2. design guidelines c1 c2 c3 c5 c4 fb v dd c6 22 m f via to v ss plane via to v dd plane void in power plane 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd v ss v dd v ss v dd v dd v ss v dd v ss v ss pi6c185 r 7 cl sdram dimm spec. from chipset s
pi6c185-00 precision 1-7 clock buffer 7 ps8317a 03/22/01 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 .252 .260 .047 1.20 .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .238 .269 1 20 .169 .177 x.xx x.xx denotes controlling dimensions in millimeters 0.05 0.15 6.1 6.7 0.45 0.75 0.09 0.20 4.3 4.5 6.4 6.6 0.65 0.19 0.30 .007 .012 max pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 20-pin tssop package mechanical (l) 20-pin qsop package mechanical (q) ordering information n / p. q e r f . x a me g a k c a p l 0 0 - 5 8 1 c 6 i pz h m 5 2 1e g a k c a p p o s s t n i p - 0 2 q 0 0 - 5 8 1 c 6 i pz h m 5 2 1e g a k c a p p o s q n i p - 0 2 l a 0 0 - 5 8 1 c 6 i pz h m 0 4 1e g a k c a p p o s s t n i p - 0 2 q a 0 0 - 5 8 1 c 6 i pz h m 0 4 1e g a k c a p p o s q n i p - 0 2 .337 .344 .053 .069 .004 .010 seating plane .025 bsc .007 .010 .228 .244 .150 .157 1 20 .016 .050 x.xx x.xx denotes dimensions in millimeters 0.635 8.56 8.74 1.35 1.75 5.79 6.19 0.41 1.27 0.101 0.254 .008 .012 0.203 0.305 3.81 3.99 0.178 0.254 .058 1.47 .015 x 45? 0.38 ref
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